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Figure 18: Ultra DMA Data-Out Burst Device Termination Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.5.4.4.10 Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in Figure 19: Ultra DMA Data-Out Burst Host
Termination Timing while timing parameters are specified in Table 26: Ultra DMA Data Burst Timing Requirements
and timing parameters are described in Table 27: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
b) The host shall assert STOP no sooner than t SS after it last generated an HSTROBE edge. The host shall not
negate STOP again until after the Ultra DMA burst is terminated.
c)
The device shall negate DMARQ within t LI after the host asserts STOP. The device shall not assert DMARQ
again until after the Ultra DMA burst is terminated.
d) The device shall negate – DDMARDY within t LI after the host has negated STOP. The device shall not assert –
DDMARDY again until after the Ultra DMA burst termination is complete.
e) If HSTROBE is negated, the host shall assert HSTROBE within t LI after the device has negated DMARQ. No
data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
f)
The host shall place the result of its CRC calculation on D[15:0] (see 6.5.4.5 ).
g) The host shall negate – DMACK no sooner than t MLI after the host has asserted HSTROBE and STOP and the
device has negated DMARQ and – DDMARDY, and no sooner than t DVS after placing the result of its CRC
calculation on D[15:0].
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 39 of 102
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